Speaker: Yiyu Shi Missouri University of Science and Technology, USA
Time: 2012-05-17 14:00-2012-05-17 15:00
Venue: FIT 1-222
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Abstract:
Accurate and efficient load current profiling is critical in on-chip power grid design problems such as the decoupling capacitance budgeting, where a noise bound may not be exceeded under all possible input scenarios. Similarly, power demand profiling is essential in smart grid related problems such as contingency-constrained economic dispatch, where N-1 contingency constraints are enforced under all possible demand. The synergies between the two problems offer the opportunity for algorithm sharing - from the well-developed on-chip power grid to the emerging smart grid. In this talk, I will first present a statistical load profiling algorithm emerged in the decoupling capacitance budgeting, and then discuss how it can be extended to enhance the quality of the economic dispatch in the smart grid.
Short Bio:
Dr. Yiyu Shi received his B.S. degree in Electronic Engineering from Tsinghua University, Beijing, China in 2005, the M.S and Ph.D. degree in Electrical Engineering from the University of California, Los Angeles in 2007 and 2009 respectively. In Sept. 2010, he joined the faculty of Electrical and Computer Engineering Department at Missouri University of Science and Technology (formerly University of Missouri, Rolla) as an assistant professor, and is currently the site associate director of National Science Foundation I/UCRC Net-Centric Software and Systems Center. He has served on the technical program committee of several top conferences including ICCAD, ICCD, and ISPD, and as guest editor (in-chief) for a few international journals. His research interest include advanced design and test technologies for 3D ICs, and smart grid applications. In recognition of his research, five of his papers have been nominated for the Best Paper Award in top conferences (DAC'05, ICCAD'07, ICCD'08, ASPDAC'09, DAC'09). He was also the recipient of the IBM Invention Achievement Award in 2009, and the second placer winner of the TAU power grid analysis contest (sponsored by IBM) in 2011, and the third place winner of the ISPD discrete gate sizing contest in 2012. For more details, please visit http://ece.mst.edu/~yshi
