Driven by the demand for higher overall performance in general-purpose processing, fast simulation of next-generation designs is critical. Architects need to understand the potential performance benefits of new techniques as well as the energy- and power-trade-offs that need to be made to accelerate general-purpose workloads. This becomes increasingly important as datacenters continue to grow size, IoT devices proliferate, and as designers consider open-source solutions as an alternative to commercial ones. The number of potential architects is increasing overall, but their tools have-not been keeping pace.Building enhanced processors takes a significant amount of time and effort and the cycle-level, detailed simulation needed to predict simulator performance can be 1000x to 10,000x slower than real-time execution. We cannot wait for others to build this promising future of high-performance, energy-efficient designs. What is needed are techniques to significantly speed up the design of these new, promising designs, while maintaining accuracy and generality. Many solutions have been proposed to help solve this bottleneck, such as analytical modeling, and even FPGA-based acceleration. But, many of these techniques are unable to keep up with the complexity, the number of processors in the system, or the features that those methodologies can simulate. Other techniques restrict the type of changes that can be investigated or complexity of the workload. In the end, we need flexible solutions that allow for scalability and flexibility, while maintaining simulation performance.In this talk, we detail our latest work on hardware virtualization-accelerated simulation that attempts to address many of these issues. In addition, we will discuss the needs for future simulation systems, as well as discuss a number of future projects that we have just begun to work on, from efficient and secure processors, to AI accelerators.
Trevor E. Carlson is an assistant professor at the National University of Singapore (NUS). He received his B.S. and M.S. degrees from Carnegie Mellon University in 2002 and 2003, his Ph.D. from Ghent University in 2014, and has worked for 3 years as a postdoctoral researcher at Uppsala University in Sweden until 2017. He has also spent a number of years working in or with industry, at IBM from 2003 to 2007, at the imec research lab from 2007 to 2009, and with the Intel ExaScience Lab from 2009 to 2014. Overall, he has over 16 years of computer systems and architecture experience in both industry and academia. Trevor Carlson’s research interests include a number of areas of computer architecture including highly-efficient microarchitectures, performance modeling and fast and scalable simulation methodologies, secure processor designs and efficient accelerator design. His goal is to improve the performance, efficiency and security of next-generation processors, covering applications that target edge (IoT) and cloud-scale applications. While a staff engineer at IBM, he helped to author 4 issued patents. During his PhD, in collaboration with the Intel ExaScience Lab, he co-developed the Sniper Multi-core Simulator which is being used by hundreds of researchers to evaluate the performance and power-efficiency of next generation systems, and continues to be used to explore next-generation processor design at Intel today. He recently worked to develop processor architectures to more efficiently handle long-latency memory accesses (Memory Level Parallelism, or MLP). Dr. Carlson’s research has been published at leading journals and conferences in computer architecture and simulation such as the International Symposium on Computer Architecture (ISCA), the International Symposium on Microarchitecture (MICRO), the International Symposium on High Performance Computer Architecture (HPCA) and the IEEE Transactions on Computers (TC). He is a recipient of the Best Paper Award at the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) in 2016, and the Best Paper Award at the International Symposium on Performance Analysis of Systems and Software (ISPASS) in 2013. In addition, his work has received four Best Paper Award nominations, one at MICRO 2019, and three at ISPASS in 2018, 2015 and 2014.