Introduction to Artificial Intelligence Chip：From Verilog to FPGA
This is a course focusing both on theoretical and experimental hardware fundamentals. The target is to implement small scale convolution operation in CNN on FPGA. After the course, students should be able to handle: How to divide control logics and computing logics. How to implement logics, timing, state-machine etc. Able to make testbenches. Able to map to FPGA, and debug on it. Know basics about back-end about ASIC chip design, like verification, layout etc. Able to implement a 3*3 convolution layer, and finish the local memory, global memory.