Cellular neural networks (CeNNs) have been widely adopted in image processing tasks. Existing researches on CeNNs have focused on the improvement of accuracy with little attention to the actual cost of hardware. This may not be a problem for server or cloud based applications, but for edge computing, hardware resource becomes the fundamental constraints. Among various hardware implementations of CeNNs emerged in the literature, Field Programmable Gate Array (FPGA) is one of the most popular choices due to its high flexibility and low time-to-market. However, existing FPGA implementations of CeNNs are typically bounded by the limited number of embedded multipliers available therein, while the vast number of Logic Elements (LEs) and registers are never utilized. Apparently, such unbalanced resource utilization leads to sub-optimal CeNN performance and speed. In this talk we will present an incremental quantization based approach for the FPGA implementation of CeNNs. It quantizes the numbers in CeNN templates to powers of two, so that complex and expensive multiplications can be converted to simple and cheap shift operations, which only require a minimum number of registers and LEs. Experimental results on FPGAs show that our approach can significantly improve the resource utilization, and as a direct consequence a speedup of 1.2x-7.8x can be achieved with no performance loss compared with the state-of-the-art implementations.
Dr. Yiyu Shi is currently an associate professor in the Department of Computer Science and Engineering and Electrical Engineering (concurrent appointment) at the University of Notre Dame. He received his B.S. degree (with honor) in Electronic Engineering from Tsinghua University, Beijing, China in 2005, the M.S and Ph.D. degree in Electrical Engineering from the University of California, Los Angeles in 2007 and 2009 respectively. He was an assistant professor in the Electrical and Computer Engineering Department at Missouri University of Science and Technology from 2010 to 2015, where he was the site founding co-director of the NSF I/UCRC Net-Centric Software and Systems Center. His current research interests include low-power design, three-dimensional integration, hardware security and renewable energy applications. In recognition of his research, eight of his papers have been nominated for the Best Paper Award and one paper have received the Best Paper in Track, all in top conferences. He was also the recipient of IBM Invention Achievement Award in 2009, Japan Society for the Promotion of Science (JSPS) Faculty Invitation Fellowship, Humboldt Research Fellowship, IEEE St. Louis Section Outstanding Educator Award, Academy of Science (St. Louis) Innovation Award, Missouri S&T Faculty Excellence Award, NSF CAREER Award, IEEE Region 5 Outstanding Individual Achievement Award, all in 2014, and the Air Force Summer Faculty Fellowship in 2015 and 2016. He has served on the technical program committee of many international conferences. He is also on the editorial board of IEEE Trans. CAD, ACM JETC, VLSI Integration, IEEE VLSI CAS Newsletter, IEEE TCCCPS Newsletter and ACM SIGDA Newsletter.